Many system-on-chip (SOC) applications and most microelectronic applications require the use of logic circuitry and memory circuitry simultaneously on the same integrated circuit chip. All stand-alone memory chips have both memory and logic together on them. The logic and memory devices and structures are usually quite dissimilar. One common example of memory use is for non-volatile or long retention time storage of data. Many applications, such as mobile communications and others requiring local storage of microcode, require the existence of non-volatile memory and logic circuitry simultaneously. Such applications, which load programs on boot-up, are becoming ubiquitous. Such circuits, most of which are examples of systems-on-chip, require complex processing because of the different ways that logic and memory circuitry are implemented. In addition, as device dimensions have decreased, silicon-on-insulator (SOI) technology has become more popular and is expected to be a mainstream technology at gate lengths below 70 nanometers (nm). Conventional front-floating gate memory structures do not scale effectively due to gate-stack thickness limitations and due to inefficient coupling of hot carriers to front floating gates.
Carrier trapping through defects and interface states in oxide-nitride-oxide (ONO) stacked films has been successfully utilized in non-volatile memory devices for the past four decades. Injection of charge in these devices can be achieved by Fowler-Nordheim (FN) tunneling or hot electron injection. Removal of charge is usually by Fowler-Nordheim tunneling. In recent years, as transistor dimensions have been scaled and technology has become more complex, there has been increased interest in these devices because of attributes expected from a large interface-state density with highly localized trapping that may be distinctly different from those of nanocrystals. Advantages include thinner gate-stacks, long retention times, reasonably low power and high endurance. However, due to the structure of the conventional ONO-based memory device, the presence of a trapping layer between the channel of the device and the gate imposes restrictions on scaling of these devices because of the interdependence of electrostatics, voltages needed for adequate programming, speed, capture cross-sections, erasing speed and non-volatility.
Accordingly, there is a need for new devices and methods of fabrication that overcome one or more of the above drawbacks.